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[Windows Develop] aa

Description: Verilog实现运算器ALU的编程，加减（16位）乘除（16*16，32/16）-Verilog to achieve calculator ALU programming, and (16) and (16*16, 32/16)
Platform: | Size: 13312 | Author: arvin | Hits:

[VHDL-FPGA-Verilog] FloatALU

Description: 用Verilog HDL实现的IEEE754浮点数加减乘除法器-float number alu
Platform: | Size: 6387712 | Author: 糊糊 | Hits:

[ARM-PowerPC-ColdFire-MIPS] CPU

Description: 用Verilog实现的 哈佛结构的简单指令集CPU程序，由ALU、地址译码器、指令译码器等部分组成-Part of a simple instruction Verilog realize the Harvard architecture CPU program set by the ALU, address decoder, an instruction decoder, etc.
Platform: | Size: 4096 | Author: qiaozhitong | Hits:

[VHDL-FPGA-Verilog] ALU_VERILOG_COCOTB

Description: ALU written in Verilog HDL and tester written in python using the cocotb library
Platform: | Size: 3072 | Author: Nobunaga Chipotle | Hits:

[VHDL-FPGA-Verilog] ALU_4_operations

Description: unid logic aritmetic- four options
Platform: | Size: 81968 | Author: fitnowredribbon | Hits:

[VHDL-FPGA-Verilog] 计算器

Description: 用verilog语言实现了一个计算器alu，实现加减乘除的简单计算。(Using Verilog language to achieve a simple calculator ALU, computing add, subtract, multiply and divide.)
Platform: | Size: 1024 | Author: 哈皮Q | Hits:
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